Self-aligned contacts

ABSTRACT

A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is a divisional of and claims the benefit ofpriority to U.S. application Ser. No. 12/755,752, which was filed onApr. 7, 2010. The entire contents of U.S. application Ser. No.12/755,752 are incorporated herein by reference.

BACKGROUND

Aspects of the present invention are directed to gate structures havingat least partial silicidation.

In typical complementary-metal-oxide-semiconductor (CMOS) transistors,metal contacts and polysilicon gates have pitches that have becomeincreasingly small over time as spatial and power requirements haveevolved. As device pitch has decreased, a need to produce smaller andsmaller spaces between metal contacts and polysilicon gates has becomeincreasingly important. However, producing small spaces using thecurrent photolithography alignment processes has proven to be prone toshort circuits and other similar failures.

A short circuit in a gate structure may be caused, in some cases, by thecontact vias at one of the source or the drain region contacting thegate. This is especially likely where the gate pitch is relativelysmall. One solution to this problem has been to fully encapsulate thegate to thereby prevent contact between the gate and the contact vias.Unfortunately, this solution results in the gate structure as a wholehaving a very high gate resistance and slow switch timing. In a memorydevice, which does not require fast switching capability, this is lessof a drawback. However, in a logic device, which requires fast switchingcapability, fully encapsulated gate structures are less useful.

SUMMARY

In accordance with an aspect of the invention, a method of forming agate structure with a self-aligned contact is provided and includessequentially depositing a sacrificial layer and a secondary layer ontopoly-Si disposed at a location of the gate structure, encapsulating thesacrificial layer, the secondary layer and the poly-Si, removing thesacrificial layer through openings formed in the secondary layer andforming silicide within at least the space formally occupied by thesecondary layer.

In accordance with another aspect of the invention, a method of forminga gate structure with a self-aligned contact is provided and includesencapsulating a location of a gate structure of a channel extendingbetween source and drain regions with lateral spacers and a secondarylayer, forming silicide at the source and drain regions and introducinga conductive material into the encapsulated location through openingsformed in the secondary layer.

In accordance with another aspect of the invention, a transistor gate isprovided and includes a channel extending between source and drainregions, a gate structure disposed on the channel between the source anddrain regions and having at least partial silicidation for aself-aligned contact, an encapsulation assembly to fully encapsulate thegate structure in lateral and radial directions, conductive elementselectrically coupled with silicide formed at the source and drainregions and an insulator having an etch chemistry different from that ofthe encapsulation assembly, which is substantially entirely interposedbetween the encapsulation assembly and the conductive elements.

BRIEF DESCRIPTIONS OF THE SEVERAL VIEWS OF THE DRAWINGS

The subject matter regarded as the invention is particularly pointed outand distinctly claimed in the claims at the conclusion of thespecification. The foregoing and other aspects, features, and advantagesof the invention are apparent from the following detailed descriptiontaken in conjunction with the accompanying drawings in which:

FIG. 1 is an example of a transistor gate structure in accordance withembodiments of the invention;

FIG. 2 is an example of a transistor gate structure in accordance withembodiments of the invention;

FIG. 3 shows a partial process of forming the transistor gate structureof FIG. 2;

FIG. 4 shows a partial process of forming the transistor gate structureof FIG. 2; and

FIG. 5 is another example of a transistor gate structure in accordancewith embodiments of the invention.

DETAILED DESCRIPTION

With reference to FIGS. 1 and 2, a gate structure including at leastpartial silicidation for a self-aligned contact is provided. Moreparticularly, a transistor gate 10 is provided and includes a substrate20, such as a silicon substrate formed as a channel, extending between asource region 30 and a drain region 40, a gate structure 50, anencapsulation assembly 60, conductive elements 70 and an insulator 110.The gate structure 50 is disposed on the substrate 20 between the sourceand drain regions 30, 40 and includes at least partial silicidation 80(in FIG. 1), 90 (in FIG. 2). The encapsulation assembly 60 fullyencapsulates the gate structure 50. The conductive elements 70 includecontact vias 75 that are electrically coupled with additional silicide76 formed on the substrate 20 at the source and drain regions 30 and 40.

The conductive elements 70 are insulated from the gate structure 50 by asecondary layer 55, which will be described below, the encapsulationassembly 60 and the insulator 110. In particular, the secondary layer 55and the encapsulation assembly 60 fully encapsulate the gate structure50 in both lateral and radial (i.e., vertical) directions. That is, thesecondary layer 55 covers a top of the gate structure 50 and theencapsulation assembly encapsulates or covers all of the sides of thegate structure 50. In addition, the insulator 110 is disposed on thesecondary layer 55 and all around the encapsulation assembly 60.

The secondary layer 55, the encapsulation assembly 60 and the insulator110 may be made of any suitable electrically insulating materials aslong as the insulator 110 has a different etch chemistry from that ofeither the secondary layer 55 or the encapsulation assembly 60. As such,during etching processes, selective etching of the insulator 110 but notthe secondary layer 55 or the encapsulation assembly 60 is possible.This selective etching of the insulator 110 will not yield a shortcircuit of the transistor gate 10.

As shown in FIG. 2 and, in accordance with embodiments of the invention,the gate structure 50 may include layers of poly-Si 51 or some othersimilar composition and silicide 52. Conversely, as shown in FIG. 1 and,in accordance with embodiments of the invention, the gate structure 50may include only silicide 52 whereby the gate structure 50 is fullysilicided (FUSI). In any case, the presence of the at least partialsilicidation 80, 90 in the gate structure 50 allows for fullencapsulation of the gate structure 50 so as to prevent or substantiallyreduce an occurrence of short circuits and allows the gate structure 50to have a relatively low gate resistance, which would not otherwise bepossible. Thus, the gate structure 50 can be used in variousapplications, such as memory devices, in which slow switching isacceptable, and in logic devices, in which fast switching is required.

The level of silicidation 80, 90 can vary, as some devices require fullsilicidation (FUSI) and others require less silicidation to achieve theeffects mentioned above. In most cases, however, even the minimum levelof silicidation is substantial and generally exceeds 1-10% or more ofthe total amount of poly-Si 51. For example, in some embodiments,silicide thickness may be about 150 A (Angstroms) and, in otherembodiments, the silicide thickness may be expressed as being >20 A.

The gate structure 50 may further include a high-K gate dielectric layer53 adjacent to the substrate 20 as well as a conductive layer 54, suchas a metallic layer, adjacent to the conductive layer 53 on which thepoly-Si 51 and/or the silicide 52 are layered. The secondary layer 55,such as a layer of silicon nitride (SiN), is disposed on the poly-Si 51and/or the silicide 52. The encapsulation assembly 60 includes spacers61 and 62, such as silicon nitride/oxide (SiN or SiO₂) spacers, andsurrounds and electrically insulates the gate structure 50. Theadditional silicide 76 is formed at an exterior of the encapsulationassembly 60 in contact with the substrate 20 at the source and drainregions 30 and 40. The contact vias 75 are disposed to be electricallycoupled to the additional silicide at those locations while also beingelectrically insulated from the gate structure 50.

With reference to FIGS. 3-4 a method of forming a gate structure 50 witha self-aligned contact is provided. The method, in accordance with someembodiments, includes sequentially depositing (operation 300) asacrificial layer 100 and a secondary layer 55 onto poly-Si 51,encapsulating at least the sacrificial layer 100, the secondary layer 55and the poly-Si 51 (operation 310), removing the sacrificial layer 100through openings 102 formed in the secondary layer 55 (operation 320)and forming silicide within at least the space 101 formally occupied bythe sacrificial layer 100 (operation 330).

The method may further include forming additional silicide 76 at thesource and drain regions 30 and 40 (operation 331). The forming of thesilicide 52 and the forming of the additional silicide 76 may be coupledwith one another or decoupled, as in the case of FIG. 5 to be describedfurther below. In either of these situations, the silicide 52 and theadditional silicide 76 may be formed of similar materials or ofmaterials that are different from one another.

Once the silicide 52 and/or the additional silicide 76 are formed, themethod may further include depositing an insulator 110 onto thesecondary layer 55, around the encapsulation assembly 60, and onto theadditional silicide 76 (operation 340) such that the insulator 110completely insulates the secondary layer 55 and the encapsulationassembly 60 in both lateral and radial directions, as mentioned above.As also mentioned above, the insulator 110 should have a different etchchemistry as that of the secondary layer 55 or the encapsulationassembly 60. Contact holes 120 at the source and drain regions 30 and 40may then be opened (operation 345) and, subsequently, filled withcontact via material 130 (operation 350). The opening of the contactholes 120 may be achieved by a selective etching of the insulator 110whereby the different etch chemistry of the insulator 110 insures thatonly the insulator 110 will be removed by the etching of operation 345.As such, even if the contact holes 120 overlap with the gate structure50, the material 130 will be insulated from the gate structure 50 by thesecondary layer 55 and/or the encapsulation assembly 60, which shouldboth remain intact.

In accordance with embodiments of the invention, the sacrificial layer100 may include any substance that can be etched selectively, such aspoly germanium (Ge) or a germanium-rich film (poly SiGe). The secondarylayer 55 is an insulator, such as silicon nitride (SiN). As such, theforming of the openings 102 in the secondary layer 55 may beaccomplished by way of, for example, lithographic processes. Thelithographic processes respect a ground rule so that a minimum distancebetween the openings 102 (see FIG. 3) satisfies an aspect ratiorequirement of the silicide forming operation. With the openings 102formed, the removing of operation 320 can be achieved and may include anetching of the sacrificial layer 100 (operation 321). In someembodiments, the etchant may include hydrogen peroxide (H₂O₂) or someother similar composition. In particular, the etchant may be non-HFbased so as to eliminate the need for a protective layer for nearbyelectronics.

The forming of the silicide 52 of operation 330 may include at least oneof atomic layer deposition (ALD) or chemical vapor deposition (CVD) ofsilicide forming material, such as tungsten (W), platinum (Pt), titanium(Ti), cobalt (Co), nickel (NI) or tantalum (Ta). Deposition is followedby an annealing of the silicide forming material to generate thesilicide 52. The annealing process may then be followed by removal ofexcess silicide forming material. In particular, it is seen that ALDprovides an option of filling the space 101 by way of the openings 102even where the openings are characterized as having relatively highaspect ratios (i.e., the openings are relatively long and thin).

With reference to FIG. 5, a gate structure 500 is shown and formed inaccordance with further embodiments of the invention. Here, the methodincludes encapsulating a location of the gate structure 500 of asubstrate 20 extending between source and drain regions 30, 40 with anencapsulation assembly 60 of lateral spacers 61, 62 and a secondarylayer 55. The method further includes forming silicide 501 at the sourceand drain regions 30, 40, and introducing a conductive material 502 intothe encapsulated location through openings 102 formed in the secondarylayer 55, substantially as described above. In addition, the methodincludes partially forming the gate structure 500 by forming a high-Kgate dielectric layer 53 adjacent to the nanowire 20, forming aconductive layer 54 adjacent the high-K gate dielectric layer 53 andproviding poly-Si 51 adjacent to the conductive layer 54. Space 101 istherefore defined between the poly-Si 51 and the secondary layer 55 andthe introducing is achieved by at least one of atomic layer deposition(ALD) and chemical vapor deposition (CVD) with respect to the space 101.

When completed, the gate structure 500 can be insulated by the secondarylayer 55, the lateral spacers 61, 62 and an insulator 110 in lateral andradial dimensions. As above, the insulator 110 should have a differentetch chemistry from that of the secondary layer 55 or the spacer 61, 62so that selective etching of the insulator 110 is possible and shortcircuits are avoided.

While the disclosure has been described with reference to exemplaryembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted forelements thereof without departing from the scope of the disclosure. Inaddition, many modifications may be made to adapt a particular situationor material to the teachings of the disclosure without departing fromthe essential scope thereof. Therefore, it is intended that thedisclosure not be limited to the particular exemplary embodimentdisclosed as the best mode contemplated for carrying out thisdisclosure, but that the disclosure will include all embodiments fallingwithin the scope of the appended claims.

1. A transistor gate, comprising: a channel extending between source anddrain regions; a gate structure disposed on the channel between thesource and drain regions and having at least partial silicidation for aself-aligned contact; an encapsulation assembly to fully encapsulate thegate structure in lateral and radial directions; conductive elementselectrically coupled with silicide formed at the source and drainregions; and an insulator having an etch chemistry different from thatof the encapsulation assembly, which is substantially entirelyinterposed between the encapsulation assembly and the conductiveelements.
 2. The transistor gate according to claim 1, wherein the gatestructure comprises poly-Si and silicide.
 3. The transistor gateaccording to claim 1, wherein the gate structure is fully silicided(FUSI).
 4. A transistor gate, comprising: a channel; a gate structuredisposed on the channel and having at least partial silicidation for aself-aligned contact; an encapsulation assembly to fully encapsulate thegate structure in lateral and radial directions; conductive elementselectrically coupled with silicide; and an insulator having an etchchemistry different from that of the encapsulation assembly, which issubstantially entirely interposed between the encapsulation assembly andthe conductive elements.
 5. The transistor gate according to claim 1,wherein the gate structure comprises poly-Si and silicide.
 6. Thetransistor gate according to claim 1, wherein the gate structure isfully silicided (FUSI).